Achieving a satisfactory yield of integrated circuit components is becoming increasing difficult in a manufacturing environment in which the number of devices or modules is ever-increasing and the geometries of those devices or modules is ever-decreasing. Conventionally to achieve satisfactory yields, design engineers implement a technique known as design for testability, which incorporates additional hardware designed purely for testing purposes into integrated circuit designs to alleviate the complexity of test pattern generation and increase test coverage. Scan design, a commonly used design for testability technique for testing sequential design, reduces the automatic test pattern generation complexity by providing implicit control and observability of the flip-flop states.
The scan design is achieved by adding a test mode to the integrated circuit design such that when the integrated circuit is in the test mode, all flip-flops are interconnected into chains and act as shift registers. In the test mode, the flip-flops can be set to an arbitrary state by shifting the logic states through the shift register. Similarly, the states can be observed by shifting the contents of the shift registers out. Thus, the inputs and outputs of the flip-flops act like primary inputs and primary outputs of the design and the combinational logic between the flip-flops can be tested with simpler methods used typically for combinational circuits. However, any fault present in the scan design makes fault diagnosis difficult, because the fault can mask out all scan cells in the same scan chain. Consequently, when scan design faults are combined with potential combinational logic faults, the fault diagnosis process can become even more complex and can result in at least a sixty percent integrated circuit chip yield loss for early processes and a similarly significant integrated circuit chip yield loss for mature processes.